The continuous shrinking in dimensions of electronic devices utilized in ultra-large scale semiconductor integrated (ULSI) circuits in recent years has resulted in increasing the resistance of the back-end-of-the-line (BEOL) metallization without concomitantly decreasing the interconnect capacitances. Interconnects may be scaled to higher aspect ratios (a height to width ratio of typically greater than 3:1) to mitigate the resistance increases, which may lead to increased capacitances. This combined effect may increase signal delays in ULSI electronic devices.
The materials may be patterned by several patterning and sacrificial masking materials which may include photoresist polymers, via fill materials. Following the lithographic patterning of the masking layer, a series of etching steps may be employed to transfer the pattern from the photoresist to each of the layers underneath, including the insulating layer. The patterning of insulating materials may require as many as seven layers, some of which may be removed after patterning, resulting in a complex and inefficient process.
It would thus be highly desirable to provide a material which can reduce the integration complexity and processing steps required, and does not require costly photoresist polymers and/or significantly reduces etching processes.